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HUFA76413DK8T
January 2003
HUFA76413DK8T
N-Channel Logic Level UltraFET(R) Power MOSFET 60V, 4.8A, 56m
General Description
These N-Channel power MOSFETs are manufactured using the innovative UltraFET(R) process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching convertors, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery-operated products.
Applications
* Motor and Load Control * Powertrain Management
Features
* * * * 150C Maximum Junction Temperature UIS Capability (Single Pulse and Repetitive Pulse) Ultra-Low On-Resistance rDS(ON) = 0.049, VGS = 10V Ultra-Low On-Resistance rDS(ON) = 0.056, VGS = 5V
D1 (8)
D1 (7)
D2 (6)
D2 (5)
1
SO-8
S1 (1) G1 (2) S2 (3) G2 (4)
MOSFET Maximum Ratings TA = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 25oC, VGS = 5V) Continuous (TC = 125oC, VGS = 5V, RJA = 228oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 5.1 4.8 1 Figure 4 260 2.5 0.02 -55 to 150 A A A A mJ W W/oC
oC
Ratings 60 16
Units V V
Thermal Characteristics
RJA RJA RJA Thermal Resistance Junction to Ambient SO-8 (Note 2) Thermal Resistance Junction to Ambient SO-8 (Note 3) Thermal Resistance Junction to Ambient SO-8 (Note 4) 50 191 228
o o
C/W C/W
oC/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2003 Fairchild Semiconductor Corporation Rev. B
HUFA76413DK8T
Package Marking and Ordering Information
Device Marking 76413DK8 Device HUFA76413DK8T Package SO-8 Reel Size 330mm Tape Width 12mm Quantity 2500 units
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 50V VGS = 0V VGS = 16V TA = 150oC 60 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A ID = 5.1A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 4.8A, VGS = 5V ID = 4.8A, VGS = 5V TA = 150oC 1 0.041 0.048 0.091 3 0.049 0.056 0.106 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(5) Qg(TH) Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge (VGS = 5V) VDD = 30V, ID = 1A VGS = 5V, RGS = 16 10 19 45 27 44 108 ns ns ns ns ns ns VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 30V ID = 4.8A Ig = 1.0mA 620 180 30 18 10 0.6 1.8 5 23 13 0.8 pF pF pF nC nC nC nC nC
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 4.8A ISD = 2.4A ISD = 4.8A, dISD/dt = 100A/s ISD = 4.8A, dISD/dt = 100A/s 1.25 1.0 43 55 V V ns nC
Notes: 1: Starting TJ = 25C, L = 20mH, IAS = 5.1A 2: RJA is 50 oC/W when mounted on a 0.5 in2 copper pad on FR-4 at 1 second. 3: RJA is 191 oC/W when mounted on a 0.027 in2 copper pad on FR-4 at 1000 seconds. 4: RJA is 228 oC/W when mounted on a 0.006 in2 copper pad on FR-4 at 1000 seconds.
(c)2003 Fairchild Semiconductor Corporation
Rev. B
HUFA76413DK8T
Typical Characteristics TA = 25C unless otherwise noted
1.2 6
POWER DISSIPATION MULTIPLIER
1.0 -ID, DRAIN CURRENT (A)
VGS = 10V, RJA=50oC/W 4
0.8
0.6
0.4
2
0.2
VGS = 5V, RJA=228oC/W 0 0 25 50 75 100 125 150 25 50 TA , AMBIENT TEMPERATURE (oC) 75 100 125 TA, CASE TEMPERATURE (oC) 150
0
Figure 1. Normalized Power Dissipation vs Ambient Temperature
4 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
1 THERMAL IMPEDANCE ZJA, NORMALIZED
RJA=50oC/W
0.1
PDM VGS = 10V 0.01 t1 t2 SINGLE PULSE 0.001 10-5 10-4 10-3 10-2 10-1 100 101 102 103 t, RECTANGULAR PULSE DURATION (s) NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA
Figure 3. Normalized Maximum Transient Thermal Impedance
300 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION RJA=50oC/W TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: VGS = 5V I = I25 175 - TA 150
IDM, PEAK CURRENT (A)
100
10
VGS = 10V
2 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103
Figure 4. Peak Current Capability
(c)2003 Fairchild Semiconductor Corporation
Rev. B
HUFA76413DK8T
Typical Characteristics TA = 25C unless otherwise noted
200 100 IAS, AVALANCHE CURRENT (A) 10 ID, DRAIN CURRENT (A) 15 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100s
10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 SINGLE PULSE TJ = MAX RATED TA = 25oC 0.2 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100
STARTING TJ = 25oC
10ms
STARTING TJ = 150oC
1 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 40
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
25
25 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
VGS = 10V 20
VGS = 5V VGS = 3.5V
ID , DRAIN CURRENT (A)
20
15 TJ = 150oC 10 TJ = 25 C 5
o
15 VGS = 3V 10 TA = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
TJ = -55oC
5
0 1.5 2.0 2.5 3.0 3.5 VGS , GATE TO SOURCE VOLTAGE (V) 4.0
0 0 0.5 1.0 1.5 VDS , DRAIN TO SOURCE VOLTAGE (V) 2.0
Figure 7. Transfer Characteristics
100 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 90 ID = 5.1A 80 2.0
Figure 8. Saturation Characteristics
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.5
70
60 ID = 1A 50
1.0
VGS = 10V, ID =5.1A 40 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) 0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2003 Fairchild Semiconductor Corporation
Rev. B
HUFA76413DK8T
Typical Characteristics TA = 25C unless otherwise noted
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.2 ID = 250A
1.0
1.1
0.8
1.0
0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
2000 1000 C, CAPACITANCE (pF) CISS = CGS + CGD
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 30V 8
CRSS = CGD 100 COSS CDS + CGD
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 4.8A ID = 1A 0 5 10 Qg, GATE CHARGE (nC) 15 20
2
VGS = 0V, f = 1MHz 10 0.1 1 10 60 VDS , DRAIN TO SOURCE VOLTAGE (V) 0
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Currents
150 VGS = 5V, VDD = 30V, ID = 1A td(OFF) SWITCHING TIME (ns) 100
tf 50 tr td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
Figure 15. Switching Time vs Gate Resistance
(c)2003 Fairchild Semiconductor Corporation
Rev. B
HUFA76413DK8T
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS
+
IAS 0.01 0 tAV
Figure 16. Unclamped Energy Test Circuit
Figure 17. Unclamped Energy Waveforms
VDS RL
VDD VDS
Qg(TOT)
VGS = 10V VGS
+
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
DUT Ig(REF)
Figure 18. Gate Charge Test Circuit
Figure 19. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH
90% 50%
Figure 20. Switching Time Test Circuit
Figure 21. Switching Time Waveforms
(c)2003 Fairchild Semiconductor Corporation
Rev. B
HUFA76413DK8T
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A = ----------------------------P DM RJA
300 RJA = 103.2 - 24.3 250
* ln(AREA)
228 oC/W - 0.006in2 191 oC/W - 0.027in2
R, RJA (oC/W)
200 150 100 50
(EQ. 1)
In using surface mount devices such as the SO-8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 22 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 22 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
R = 46.4 - 21.7 * ln(AREA)
0 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) PER DIE
Figure 22. Thermal Resistance vs Mounting Pad Area
R JA = 103.2 - 24.3 ln ( Area )
(EQ. 2)
The dual die SO-8 package introduces an additional thermal coupling resistance, RB. Equation 3 describes RB as a function of the top copper mouting pad area.
R B = 46.4 - 21.7 ln ( Area )
(EQ. 3)
The thermal coupling resistance vs. copper area is also graphically depicted in Figure 22.
(c)2003 Fairchild Semiconductor Corporation
Rev. B
HUFA76413DK8T
PSPICE Electrical Model
.SUBCKT HUFA76413DK8T 2 1 3 ; CA 12 8 7.8e-10 CB 15 14 9.8e-10 CIN 6 8 5.8e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 67.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.34e-9 LSOURCE 3 7 0.59e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 22.5e-3 RGATE 9 20 2.2 RLDRAIN 2 5 10 RLGATE 1 9 13.4 RLSOURCE 3 7 5.9 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 15.3e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1 RLGATE CIN
rev April 2002
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2.5))} .MODEL DBODYMOD D (IS = 8e-13 RS = 1.58e-2 TRS1 = 1e-3 TRS2 = 3e-6 XTI=3.2 CJO = 8e-10 TT = 3.2e-8 M = 0.54) .MODEL DBREAKMOD D (RS = 1.18 TRS1 = 2e-3 TRS2 = -2.6e-5) .MODEL DPLCAPMOD D (CJO = 5.7e-10 IS = 1e-30 N = 10 M = 0.87) .MODEL MMEDMOD NMOS (VTO = 1.68 KP = 2 IS =1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.2) .MODEL MSTROMOD NMOS (VTO = 2.05 KP =35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.15e-3 TC2 = -7.5e-7) .MODEL RDRAINMOD RES (TC1 = 8.5e-3 TC2 = 1.2e-5) .MODEL RSLCMOD RES (TC1 = 3e-2 TC2 = 5.3e-7) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.4e-3 TC2 = -7e-6) .MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 2e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.0 VOFF= -1.0) VON = -1.0 VOFF= -5.0) VON = -0.2 VOFF= 0.2) VON = 0.2 VOFF= -0.2)
(c)2003 Fairchild Semiconductor Corporation
+
DBODY
Rev. B
HUFA76413DK8T
SABER Electrical Model
REV April 2002 template HUFA76413DK8T n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 8e-13, rs = 1.58e-2, trs1 = 1e-3, trs2 = 3e-6, xti = 3.2, cjo = 8e-10, tt = 3.2e-8, m = 0.54) dp..model dbreakmod = (rs = 1.18, trs1 = 2e-3, trs2 = -2.6e-5) dp..model dplcapmod = (cjo = 5.7e-10, isl =10e-30, nl =10, m = 0.87) m..model mmedmod = (type=_n, vto = 1.68, kp = 2, is =1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.05, kp = 35, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.48, kp = 0.04, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.0, voff = -1.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.0, voff = -5.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.2)
DPLCAP 5 RLDRAIN
LDRAIN DRAIN 2
c.ca n12 n8 = 7.8e-10 c.cb n15 n14 = 9.8e-10 c.cin n6 n8 = 5.8e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod
ESG
10 RSLC1 51 RSLC2 ISCL 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 6 MSTRO 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY
i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.34e-9 l.lsource n3 n7 = 0.59e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 17 18 RVTEMP 19 IT VBAT + 8 RVTHRES 22
S1A S2A res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = -7.5e-7 12 15 13 14 res.rdrain n50 n16 = 22.5e-3, tc1 = 8.5e-3, tc2 = 1.2e-5 8 13 res.rgate n9 n20 = 2.2 S1B S2B res.rldrain n2 n5 = 10 13 CB res.rlgate n1 n9 = 13.4 CA + 14 + res.rlsource n3 n7 = 5.9 6 5 res.rslc1 n5 n51= 1e-6, tc1 = 3e-2, tc2 =5.3e-7 EGS EDS 8 8 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 15.3e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 2e-7 res.rvthres n22 n8 = 1, tc1 = -1.4e-3, tc2 = -7e-6
spe.ebreak n11 n7 n17 n18 = 67.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5)) } }
(c)2003 Fairchild Semiconductor Corporation
Rev. B
HUFA76413DK8T
SPICE Thermal Model
REV April 2002 HUFA76413DK8T Copper Area = 0.493in2 CTHERM1 th 8 8.5e-4 CTHERM2 8 7 1.8e-3 CTHERM3 7 6 5.0e-3 CTHERM4 6 5 1.3e-2 CTHERM5 5 4 4.0e-2 CTHERM6 4 3 1.5e-1 CTHERM7 3 2 7.5e-1 CTHERM8 2 tl 3 RTHERM1 th 8 3.5e-2 RTHERM2 8 7 6.0e-1 RTHERM3 7 6 2 RTHERM4 6 5 8 RTHERM5 5 4 18 RTHERM6 4 3 20 RTHERM7 3 2 23 RTHERM8 2 tl 25
th JUNCTION
RTHERM1 8
CTHERM1
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
SABER Thermal Model
SABER thermal model HUFA76413DK8T Copper Area = 0.493in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =8.5e-4 ctherm.ctherm2 8 7 =1.8e-3 ctherm.ctherm3 7 6 =5.0e-3 ctherm.ctherm4 6 5 =1.3e-2 ctherm.ctherm5 5 4 =4.0e-2 ctherm.ctherm6 4 3 =1.5e-1 ctherm.ctherm7 3 2 =7.5e-1 ctherm.ctherm8 2 tl =3 rtherm.rtherm1 th 8 =3.5e-2 rtherm.rtherm2 8 7 =6.0e-1 rtherm.rtherm3 7 6 =2 rtherm.rtherm4 6 5 =8 rtherm.rtherm5 5 4 =18 rtherm.rtherm6 4 3 =20 rtherm.rtherm7 3 2 =23 rtherm.rtherm8 2 tl =25 }
RTHERM4 5
CTHERM4
RTHERM5 4
CTHERM5
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
CASE
(c)2003 Fairchild Semiconductor Corporation
Rev. B
TRADEMARKS
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LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I1

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